Modern optical systems increasingly rely on digital signal processor (DSP) Complementary Metal Oxide Semiconductor (CMOS) application-specific integrated circuit (ASICs) for reliable data transmission. These systems use digital-to-analog converters (DACs) to convert digital values to analog signals. An ongoing challenge towards DAC integration in CMOS technology is a requirement to operate with increased sampling rates in each new generation of systems. For example, a recent requirement is to operate above 100 Gs/s with 8-b resolution. Presently, these requirements are beyond the feasibility of modern CMOS technologies unless an interleaving approach is used.
A time interleaved DAC architecture allows, with an interleaving ratio of at least two, extension of the sampling rate limit by a factor of two if each DAC operates close to its technology limit. However, additional issues arise. These issues are related to, for example, accurate timing alignment between the DACs and with the CMOS analog block that does time interleaving. Factors like voltage, temperature, and process variations may result in phase mismatches and performance degradation.